Microchip’s ZL30735 integrates eight DPLLs, five low-output jitter synthesizers, and an IEEE 1588-2008 protocol stack. The splitting of radio access network functions creates an Open RAN that promises greater innovation and features in 5G networks. Splitting the traditional baseband unit into radio units (RU), distribution units (DU) and centralized units (CU) brings timing issues not…
Renesas adds three timing ICs for 4G/5G radios
The 8V19N850 radio synchronizer and 8V19N880/8V19N882 jitter attenuators enhance a radio unit’s timing capabilities.
How Virtual Primary Reference Time Clocks improve 5G network timing
The 5G rollout continues to gain momentum and with it comes timing issues. As timing and transport technologies evolve and advance, they offer enhancements and alternatives to 5G timing architectures for fronthaul applications. The Virtual Primary Reference Time Clock (vPRTC) offers some advantages over traditional architectures.
CDR chip supports 50 Gbps data streams
The GN2255 clock-data recovery chip from Semtech cleans signals in 50 Gbps PAM4 data streams and integrates an optical laser driver.
Accelerate 5G telco functions in COTS servers
The T1 Telco Accelerator Card from Xilinx turns a standard server into a processor capable of handling 5G data streams.
5G changes network timing architectures
Radio-access networks are changing from a single unit into a distributed system, which impacts how networks keep time. Precision Time Protocol will distribute timing information, keeping the units synchronized in time and phase.