To meet the ever-increasing data demands of smart phone functionality, the infrastructure architecture of modern digital mobile communication systems must constantly evolve to accommodate wider bandwidths and faster data conversion. Functional processing blocks that are now being utilized in data conversion architectures to achieve faster data rates are Digital IF processing, DDC (Digital Down Converter) and DUC (Digital Up Converter). These digital functions can be realized in DSPs and FPGAs, and some big company also build their own digital IF processing ASICs. ADI is integrating more and more of these digital IF processing blocks into high-speed converter ICs, which significantly relieves design work and provides cost and power savings in the system. This article explores the integrated DDC and DUC channels in ADI’s IF and RF converters and explains how they work in real-world applications.
High speed converters are one of the key functions in modern wireless base station system. More and more such converters are integrated with complex digital signal processing blocks to simplify the FPGA’s work in the system design. Digital signal processing blocks in converters provide valuable benefits to system designs, but these benefits are still not widely understood by many engineers. This article will hopefully give a clear view of DDC and DUC functionality in data converters and enable system designers to fully utilize the benefits which ADI converters can provide to the transceiver architecture. Please note that this article will focus on digital processing blocks in ADCs and DACs, so the transmitter and receiver blocks are combined in some descriptions. Please omit the signal flow direction if it causes confusion.
In modern digital mobile communication system, the transmission and receive paths (including observation receive path in below description) can be divided into three major stages based on the signal’s properties: the RF stage, the analog IF stage, and the digital IF stage.
Figure 1 shows the block diagram of typical transmitter and receiver.
The RF stage deals with the RF signal, which generally includes the signal frequency range of 700 MHz to 3.5 GHz in the current LTE standard.
After the mixer, modulator or demodulator—which are all frequency shifting stages, the RF signal will be shifted to a lower frequency around DC, to less than 300 MHz. From the data converter to the mixer, the process module includes converters (ADC or DAC), analog filters, and IF amplifiers. We called this stage the analog IF stage.
After the converters, in fact, after the quantizer portion of the converters, the signal becomes digital, and together with the subsequent FPGA or ASIC, we called this the digital IF stage. The common term for individual digital signal processing blocks in this stage are the DUC (Digital Up Converter) for Tx path and the DDC (Digital Down Converter) for Rx path.
An exception is in a Direct RF architecture, where data converters sample RF signals directly, so analog IF stage will be omitted and the signal chain will consist of the RF stage and digital IF stage only.
A typical DDC module includes the carrier selection, frequency down converter, filter and decimator. These function blocks work in sequence or can be bypassed respectively and finally generate a complex signal at DC or a real signal based on the requirements of the following FPGA or ASIC with lower sampling rates.
A typical DUC module also includes interpolation, a filter, a frequency up converter and a carrier combiner. A DUC will generate a complex signal at DC, IF-based or RF directly depending on the system architecture design. Compared with the DDC, we will find that the processing is almost converse with that of the DDC.
Multiple stages DDCs and DUCs are often cascaded respectively for flexibility. Independent DDCs and DUCs requires dealing with multiple carriers in parallel and combining them together before outputting the transmission signal or separating them in the received signal.
In Rx chain, higher sampling rates are necessary to avoid signal aliasing, easy analog filter design and to provide wider signal band. But on the other hand, lower data rates on interface are preferred to save power, cost and high speed logics in FPGA/ASICs. The converter’s integrated DDC will address above requirements.
Figure 2 shows the block diagram of typical DDC.
To choose the desired carriers from blockers, interferences or other carriers, the output frequency of an NCO is that is mixed with input IF signal, to shift the desired carriers to DC. This will ease the complexity of the followed filter and decimator stage.
Filter and Decimation
Following the NCO and Mixer stages, a low pass filter is used to pick up the desired carriers and suppress other un-wanted signals. Following the filter, a decimator will reduce the data rate by a factor of 2 lower the data rate. To save resources and provide flexibility to customer, a half-band FIR filter plus decimator by 2 functions are combined in one block, and the block is copied and pasted to cascade 3-4 levels. System designers can choose to use some or all of them based on the application. Decimation by other number more than 2 are also used for additional flexibility especially in RF ADCs.
In Tx chain, there are the same requirements as in Rx chain, high sampling rates is desired to easy filter design, place signal on high IF or RF directly and push image far away but lower data rates are preferred for interface. The converter’s integrated DUC will address this requirements.
Figure 3 shows the block diagram of a typical DUC.
Interpolation and Filtering
The simplest digital interpolation algorithm is called zero padding, which means inserting 0 into every other samples, the sampling rate is doubled, but an image is also generated at Fs-Fif in the resulting spectrum. So following the interpolator with a filter stage is necessary to remove the image or the original carrier based on the application. If the original carrier is removed, the result is an interpolation and coarse modulation with Fs/2.
As in the DDC, the interpolation by 2 and filter are combined as a block, this functional block is then copied, pasted and cascaded 3-4 levels for flexibility. Other interpolation factors more than 2 are also used for additional flexibility especially in RF DACs.
Very similar to this block in the DDC, the following NCO+Mixer stage in the DUC are used to shift the carrier to the desired IF or RF frequency depending on the requirements of the system architecture. In a ZIF architecture, this block can be bypassed to keep the carrier at DC.
Gain, Phase, I/Q offset and Anti-Sinc
The gain, phase adjust, I/Q offset and Anti-Sinc blocks are accessories in many IF/RF DACs.
Gain and phase adjust, IQ offset are often work together to tune the output signal I/Q channel independently, compensate different kinds of I/Q mis-match cause by DAC, analog filter and modulator and finally get a perfect complex signal after analog modulator with low LO leakage and image.
Anti-Sinc filter compensate the Sinc roll-off caused by the DAC, which affect the flatness especially in wide band application on high IF or DRF architecture.
In this article, we have a brief description on typical DDC and DUC integrated in current IF/RF converters, what they are, why they are and how they work in signal chain. Understood these and make use of them properly will relieve resources and code works in FPGA/ASICs and hence save power and cost in system. Additional detailed and deep descriptions can be found in attached references.