5G networks rely on the distribution of packets at high speed between the backhaul network and the air interface. Packets must travel through switches, routers, and network-processing units. Reliable packet distribution depends on highly accurate time signals that maintain precise synchronization of network equipment from end to end.

Clocks and oscillators throughout the 5G radio access network (RAN) propagate time signals among network equipment. According to the ITU-T’s recommendations for building a transport network, a timing signal can sustain a maximum error of just ±1.5 µsec in its journey between the backhaul and the radio.

Such a small margin imposes strict demands on the systems and oscillators that maintain stable and accurate timing. At certain points in the network, the strain on these components becomes acute because environmental factors weaken frequency stability. The choice of timing components is also, in some cases, constrained by the host equipment’s physical attributes.

This article offers guidance on choosing the right criteria for evaluating timing components for a 5G RAN, particularly in the critical locations where timing accuracy is most at risk of exceeding its error budget.

How timing affects network performance
5G network technology came in response to market demands for faster downloads, stronger security, more data bandwidth, and connectivity to many more devices, both user terminals and IoT nodes. The increasing application of artificial intelligence (AI) in mobile-networked devices, backed by the introduction of multi-access edge computing (MEC), also calls for the lower latency that 5G networks deliver compared to 4G.

Two important features of 5G arise from the use of higher frequencies: the mmWave bands and a shift from frequency-division duplex (FDD) to time-division duplex (TDD) signal modulation. Both changes narrow the margin of error allowed in the timing signals synchronizing 5G payloads and network operations; specifications for jitter and frequency stability must be set much tighter than in the 4G world.

Equipment manufacturers and network operators have learned that timing components have newfound importance in their world: timing has become a fundamental enabler of the new features and capabilities that underpin 5G networks’ revenue models.

Complex architecture requires accurate synchronization

As Figure 1 shows, a packet passes through multiple nodes in a 5G RAN on its journey from the core network to the radio. Data gets routed through the core and RAN, passing through switches and routers. Mid-haul and front-haul networks can employ MEC servers to provide cloud-computing functions, such as AI, close to the end user. This minimizes latency, tightens security, and improves IoT device performance.

5G base stations that employ Open RAN technology have a new structure comprised of three functional units: the central unit (CU), distributed unit (DU), and radio unit (RU). The CU mainly implements non-real-time functions in the higher layers of the protocol stack and can attach to one or more DUs. The DU supports the lower layers of the protocol stack, including part of the physical layer. The RU includes hardware to convert radio signals into a digital stream for transmission over a packet network.

A notable innovation of 5G technology is the proliferation of small cells offering short-range, high-bandwidth connectivity at the network edge. A small cell may be a femtocell, picocell, or microcell with a range of 10 m, 200 m, or 2000 m, respectively.

Industry standards govern time
Synchronization requires a reference for time. In normal operation, this is derived from a Global Navigation Satellite Service (GNSS) radio signal, which is traceable to ultra-accurate atomic clocks running in government laboratories. Distributed throughout the network, this master time signal provides a reliable basis for synchronization.

The methods used to synchronize timing signals that propagate through the network are governed by industry standards. These standards are typically applied to equipment to make them comply with the 3GPP’s 5G specifications:

• The total end-to-end time error must be less than ±1.5 µs.
• The frequency error at the base-station air interface must be less than ±50 ppb.
• At the Ethernet physical layer, which supports packet transfer in the backhaul and mid-haul networks, Synchronous Ethernet (SyncE) provides frequency synchronization in compliance with the ITU-T G.8262 and G.8262.1 specifications.

Synchronization lets the equipment in a 5G network timestamp individual packets and downstream equipment to extract reliable time measures from these time stamps. The (PTP) provides a standard protocol for time-stamping data in a computer network.

To minimize time error, SyncE may be used to synchronize frequency between items of Ethernet networking equipment and, in combination with PTP, to synchronize the network to the GNSS time signal. For mainstream 5G RAN systems, a combination of PTP and SyncE offers the most accurate way to implement time synchronization. This timing setup, for example, lets equipment operating in ITU-T Class D mode keep time errors to under ±5 ns.

These systems normally depend on the unbroken availability of a GNSS signal to provide a reference time signal. Unfortunately, a CU or DU cannot always get access to upstream GNSS timing. In this case, they must rely on a local oscillator within a telecom grandmaster (T-GM) to maintain timing downstream for proper PTP operation.

Why timing components matter
When SyncE synchronizes to a reference time signal, timing is handed on from one node to the next. Each piece of network equipment recovers a clock signal from the data passing through it. It cleans the recovered clock, then uses this clean clock signal to time data back out onto the line.

This operation repeats down the line, from where the time signal is directly derived from the GNSS clock all the way downstream to the network edge. This recover, clean, and retransmit process ensures that downstream nodes are frequency synchronized to upstream nodes.

Such frequency synchronization uses jitter attenuators to clean the recovered clock signal. They feature a low-bandwidth phase-locked loop (PLL) operating between 1 mHz and 10 Hz to filter jitter and wander.

This attenuator also benefits from a local oscillator, providing redundancy and fault tolerance using input monitoring and hitless switching. The role of the local oscillator is to maintain an accurate time signal for a limited period if the upstream connection is temporarily lost. This holdover function is particularly important for routers, CUs, and DUs to keep the downstream network running.

The local oscillator’s holdover specification is perhaps the most important parameter for the network equipment designer to evaluate. It sets the period for which the downstream network can continue operating within its specified time-error margin in the absence of a more accurate reference clock. Figure 2 illustrates holdover by showing a local clock’s timing synchronized, or disciplined, to an upstream reference derived from GNSS timing. When this reference is lost, the local clock begins to drift in frequency with a time error, E(τ_h), at a holdover time τ_h.

At best, an oven-controlled oscillator (OCXO) typically provides holdover time for between 1 hours and 12 hours, but this type of clock is hot, bulky, and power-hungry. A system that can tolerate a shorter holdover time instead use temperature-compensated oscillators (TCXOs), which can maintain a holdover from 1 hour to 4 hours.

In the case of CUs and DUs, the nature of the hardware imposes its own constraints. These network elements are transitioning towards using off-the-shelf servers that often embed Open Compute Project (OCP) NIC 3.0 PCIe-based cards. These low-profile cards have limited height to accommodate components, which requires using thin OCXOs, less than 7 mm high, to provide holdover.

Environmental factors
PTP packets propagate throughout the network to synchronize its nodes. They might, for example, pass through a telecom boundary clock in the CU or DU and an ordinary clock in the RU.

At each node, a PTP servo disciplines a local oscillator to the time derived from network packets. Because thermal drift is the dominant source of error in the local oscillator, selecting an oscillator with excellent short-term stability is essential. This performance criterion is different from the measure most often evaluated by electronics system designers, which is frequency stability specified for the lifetime of the device.
A local oscillator will be disciplined regularly, perhaps once a second or even more frequently, making lifetime stability irrelevant. The equipment designer needs to focus on the frequency-over-temperature slope (df/dt): the steeper the slope over a given temperature rise, the greater the error introduced into the timing signal. Put the other way, oscillators with low df/dt reduce network time error, filtering more packet-delay variation (PDV) by enabling lower PTP servo bandwidths.

Temperature variation is, therefore, a significant cause of timing errors in server-based network elements such as DUs and CUs. Environmental factors can also disturb timing operations at the network edge. 5G network densification occurs through the installation of small cells in new types of locations including under manhole covers, attached to the sides of buildings, on street lamps, and elsewhere. Unlike the climate-controlled environment of a server room, these locations are exposed to high and low temperature extremes. Most radios are convection-cooled, so the outside temperature directly affects the temperature inside the enclosure.

This means that radios require local oscillators resilient to changes in temperature and therefore have a low df/dt. They must also handle temperatures ranging from -20°C to 105°C in a single design for global deployment.

Temperature is not the only environmental stressor affecting local oscillators: shock and vibration can affect radios located close to train or tram lines or busy highways, and storm winds can shake radios mounted in exposed locations, for instance, on streetlight poles. Resistance to shock and vibration is another essential criterion for the evaluation of oscillators in 5G radios.

High-performance timing: the key to 5G’s value
5G networks promise a step-change in throughput, latency, and connectivity compared to 4G. High-speed data interfaces in nodes such as CU and DU servers and switch ICs in routers make this superior performance possible. Each of these interfaces requires low-jitter clocks or oscillators that offer high immunity to power-supply noise.

Closer to the edge of the network, clocks need to provide high short-term frequency stability over temperature and withstand shock and vibration. 5G network equipment designers will profit from closely studying timing components’ datasheets. Particularly those emphasizing the importance of low-phase jitter, the ability to reject jitter caused by power-supply noise, alongside holdover, low df/dt, and excellent resistance to shock and vibration.

Gary Giust, PhD, heads technical marketing at SiTime where he enjoys participating in industry standards, architecting timing solutions and educating customers. Prior to SiTime, Giust founded JitterLabs, and previously worked at Applied Micro, PhaseLink, Supertex, Cypress Semiconductor, and LSI Logic. Giust is an industry expert on timing, has co-authored a book, is an invited speaker, an internationally published author in trade and refereed journals, and a past Technical Chair for the Ethernet Alliance’s backplane subcommittee. He holds 20 patents. Giust obtained a Doctorate from the Ira A. Fulton Schools of Engineering at Arizona State University, Tempe, a Master of Science from the College of Engineering & Applied Science at the University of Colorado Boulder, and a Bachelor of Science from the College of Engineering and Physical Sciences at the University of New Hampshire, Durham, all in electrical engineering.

Deepak Tripathi is currently Director of Product Marketing for the Communications & Enterprise Products at SiTime. Prior to SiTime, Deepak previously held product line and engineering management positions at Intel, Broadcom, and Ruckus Wireless, in addition to start-ups in Optical Networking and Imaging. Tripathi earned a Master of Business Administration from the Wharton School of the University of Pennsylvania, a Master of Science in electrical engineering from the College of Engineering at the University of Wisconsin-Madison, and a Bachelor of Engineering in computer engineering from the Department of Computer Science at the University of Mumbai.

Carl Arft, PhD, has over 20 years of experience in micro-electromechanical systems (MEMS) research and development. He is currently Senior Director of Systems Engineering at SiTime Corporation, the world leader in MEMS-based timing devices. Before SiTime, Arft served as a Faculty Fellow in the Department of Engineering at the University of California, Davis. Previously, he held technology development roles at several optical MEMS start-up companies, including C Speed Corporation and Newport Opticom. Arft received a Bachelor of Science degree in electrical engineering from Michigan Technological University and a Master of Science and Doctorate degree in electrical engineering from the College of Engineering at the University of California, Davis.