The upstream linear burst-mode transimpedance amplifier is the first to support 50 Gb/sec NRZ and 100 Gb/sec PAM4. They could drastically increase internet connection speeds and 5G infrastructure.

Researchers from IDLab — an imec research group at Ghent University and the University of Antwerp, Belgium — and Nokia Bell Labs have developed the first upstream linear burst-mode transimpedance amplifier (TIA) chip that accommodates 50 Gbit/s NRZ and 100 Gbit/s PAM-4 modulation. The chip lets optical line terminals (OLTs) cope with upstream packets’ varying signal strength and quality degradation, effects compounded by the speeds of next-generation passive optical networks (PONs). The TIA chip could make next-gen flexible 100G PON deployments technically and economically viable, according to a press release.

PON technology brings high-speed broadband to residential and business subscribers, while supporting services such as 5G fronthaul and backhaul.

PON networks operate through a tree-like network topology that serves multiple customers with a common fiber strand connected to a single OLT in an operator’s central office. This improves cost-effectiveness and impacts how packets travel the network. For example, downstream traffic is sent over the network continuously, while upstream traffic is transmitted in bursts or allocated time slots, thus preventing collisions.

Sales for 10G PON are skyrocketing and the 25G PON products are now in production. Upstream direction, make more important as people upload videos, brings challenges building 50G and 100G PONs.

Upstream packets arriving at an OLT’s receiver may present a wide optical power dynamic range to the receiver caused by the differential path loss of the optical distribution network and variations in a transmitter’s launch power. Furthermore, the distance between an OLT and its ONTs — from a few hundred meters to a few tens of kilometers — plays a role.

“As those effects are compounded even further by the high speeds at which next-gen PONs operate, it will be crucial to make sure that all packets arriving at the OLT end up having roughly the same signal strength. Moreover, this must be done with minimal overhead — i.e. no more than a few tens of nanoseconds,” said Gertjan Coudyzer, senior researcher in analog/mixed signal IC design at IDLab, an imec research group at Ghent University and the University of Antwerp. “Our novel chip does exactly that, allowing us to use each packet – and the network as a whole — to the fullest, maximizing its speed, reach and throughput.”

“During our experiments,” continued Coudyzer, “we have been able to validate the chip’s linear burst-mode operation; a linearity not only enabling signal equalization, but also paving the way for PAM-4 as a future PON modulation format — doubling the bitrate compared to the use of NRZ. This world’s first is a breakthrough to facilitate the future roll-out of large-scale 100G PONs.”

The TIA chip is fabricated in a 0.13 μm SiGe process. It consumes 275 mW (on average) from a 2.5 V supply. Its total settling time is well under 150 ns, which meets the typical PON target preamble time.